(1) Field
This invention relates to an electrostatic discharge protection circuit and a semiconductor device and, more particularly, to an electrostatic discharge protection circuit and a semiconductor device for protecting an internal circuit against overvoltage added to power supply voltage due to an electrostatic discharge.
(2) Description of the Related Art
For example, gate oxide film layers of transistors have become thinner with the progress of microfabrication technology. Accordingly, the employment of measures to prevent the breakdown of semiconductor devices caused by electrostatic discharge (ESD) has become an important subject.
An ESD protection circuit for protecting an element against ESD will now be described. FIG. 10 is a circuit diagram showing an example of an ESD protection circuit included in a conventional semiconductor device.
In this example, circuit blocks 910 and 920 to which electric power is supplied from different power supplies are located over the same semiconductor substrate. In the circuit block 910 a clamp circuit 911 for protecting an internal circuit is located between the power supply the electric potential of which is VDD1 and ground (GND) the electric potential of which is VSS. Similarly, in the circuit block 920 a clamp circuit 921 is located between the power supply the electric potential of which is VDD2 and the GND the electric potential of which is VSS.
It is assumed that a control signal used for controlling the circuit block 920 is sent via a signal line 940 as a signal outputted from the circuit block 910 to the circuit block 920. If a fixed signal is outputted as the control signal, the control signal may be fixed at a high level (electric potential of the power supply) or a low level (electric potential of the GND). In this example, the control signal is fixed at the high level.
When voltage which is far higher than ordinary voltage is applied in this state as VDD1 as a result of an ESD, an electric current path a is formed by the clamp circuit 911. An electric current flows along the electric current path a and into the GND. This prevents the production of a great electric potential difference between VDD1 and VSS and therefore prevents the dielectric breakdown of gate oxide films of two input transistors included in the circuit block 920.
A semiconductor circuit device which includes a plurality of protection circuits according to power supply system and which discharges static electricity that collects in a package to an externally connected terminal via a protection circuit is proposed (see, for example, Japanese Unexamined Patent Publication No. 9-36245 (FIG. 1)).
By the way, electrostatic discharge failure models include a machine model (MM), a human body model (HBM), and a charged device model (CDM). Studies on the MM and the HBM are advancing. For example, in the case of the MM and the HBM, standards for resistance to electrostatic discharge failure are conventionally set. A high level of breakdown voltage can be maintained by using the conventional ESD protection circuit shown in FIG. 10. In the case of the CDM, however, a high level of breakdown voltage cannot always be maintained by using the conventional ESD protection circuit because, for example, a guarantee of breakdown voltage has not been required up to recently.
The characteristics of these models, together with test circuits which simulate the models, will now be described. FIGS. 11A and 11B are views showing the rough structure of the test circuits which simulate the electrostatic discharge failure models. FIG. 11A shows the rough structure of the test circuit which simulates the MM and the HBM. FIG. 11B shows the rough structure of the test circuit which simulates the CDM.
In the case of the MM, an electric discharge occurs when a charged metal machine (robot, for example) that handles a device touches a device terminal. In the case of the HBM, an electric discharge occurs when a person's charged body directly touches a semiconductor device.
As shown in FIG. 11A, a condenser discharge method is used for simulating failures which occur in the MM and the HBM. With the condenser discharge method, an electric charge is held in a condenser C the capacitance of which corresponds to that of the person's body or the metal machine, and the electric charge held in the condenser C is discharged to a device (DUT in FIG. 11A) 950 via a resistor R by switching a relay. In the MM an electric charge collects in a metal object, so the discharge capacitance of the condenser C and the discharge resistance of the resistor R are set to, for example, 200 pF and 0Ω respectively. In the HBM an electric charge collects in a person's body, so the discharge capacitance of the condenser C and the discharge resistance of the resistor R are set to, for example, 100 pF, which corresponds to the capacitance of a person's body, and 1.5 kΩ, which corresponds to the resistance of a person's skin, respectively.
In the CDM a device itself is charged by, for example, friction with an automatic transportation machine or the like or dielectric charging from a charged object. When the charged device touches a tester, a jig, or a tool, an electric discharge occurs. As shown in FIG. 11B, a device charging method is used for simulating a failure which occurs in the CDM. With the device charging method, a DUT 950 is charged by connecting it to a power supply. An electric charge held in the DUT 950 is discharged via a resistor R the discharge resistance of which is 1Ω by switching a relay.
Compared with the MM and the HBM simulated by the condenser discharge method, the electric charge discharged flows in a very short period of time in the CDM. This is a characteristic of the CDM. The influence of these electrostatic discharge failure models on the conventional ESD protection circuit will be described.
The conventional ESD protection circuit (clamp circuit) shown in FIG. 10 prevents an ESD from generating overvoltage between VDD1 and VSS. However, at this time an electric current flows in the ESD protection circuit, resulting in IR drop (fall in voltage) caused by the ESD protection circuit.
Each of FIGS. 12A, 12B, and 12C is a view showing the waveform of a control signal in the conventional ESD protection circuit at the time of the occurrence of an ESD. FIG. 12A is a view showing the waveform of a control signal in the conventional ESD protection circuit in the case of the MM. FIG. 12B is a view showing the waveform of a control signal in the conventional ESD protection circuit in the case of the HBM. FIG. 12C is a view showing the waveform of a control signal in the conventional ESD protection circuit in the case of the CDM.
The control signal is received by the circuit block 920. In the case of the MM and the HBM shown in FIGS. 12A and 12B respectively, the control signals are comparatively wide pulse signals and their pulse widths are, for example, of the order of some tens of nanometers. Accordingly, voltage applied to the circuit block 920 does not exceed the breakdown voltage of gate oxide films. As a result, electrostatic discharge failure can be prevented fully by using the conventional ESD protection circuit.
In the case of the CDM shown in FIG. 12C, however, the control signal is a pulse signal having a very great slope. The pulse width of this control signal is about one hundredth of that of the pulse signal in the case of the MM shown in FIG. 12A. An electric current flows in a very short period of time in the CDM. Therefore, the amount of the electric current is not so large, but a peak electric current becomes powerful. As a result, there is a significant change in the voltage of the control signal. Voltage applied to the transistors included in the circuit block 920 which receives the control signal exceeds the breakdown voltage of the gate oxide films. A gate oxide film of a MOS device is thin and is about several to 100 nm thick. Therefore, when voltage higher than the breakdown voltage is applied, the gate oxide film breaks down. As a result, a dielectric breakdown of the gate oxide films of the input transistors included in the circuit block 920 which receives the control signal occurs in the CDM.
That is to say, with the conventional ESD protection circuit and semiconductor device it is difficult to prevent the breakdown of a semiconductor device caused by an electrostatic discharge in the CDM in which a pulse signal having a very great slope flows.
In addition, with the semiconductor circuit device disclosed in Japanese Unexamined Patent Publication No. 9-36245, an electric charge that collects in the package is discharged to the externally connected terminal via one of the ESD protection circuits included according to power supply system. In this case, however, the ESD protection circuits must always be connected to the externally connected terminal. This is not desirable.